This invention relates to integrated circuits, and in particular to an improved test structure for determining stress migration characteristics of conductors in integrated circuits.
The reliability of integrated circuits is a significant factor in their production and use. During the manufacturing process, process parameters are controlled to ensure high reliability in all stages of the manufacturing process. Where feasible, tests are performed at intermediate stages of production so corrective action can be taken if necessary. The importance of precise control of parameters will be appreciated when it is realized that integrated circuit manufacture requires hundreds of steps. The steps typically process one or more wafers, each containing multiple integrated circuits, or chips. Completion of all steps for each wafer typically requires several weeks. A large inventory of very valuable product is in process at any point in time. Should a process parameter be out of specification, it may be several weeks before it is discovered, thereby resulting in a significant economic loss of wafers in-process and in time to getting product to market.
One area of concern is the stress migration characteristics of traces or conductors, such as metal (e.g. aluminum, aluminum alloys, refractory metal, copper, copper alloys, gold, gold alloys, silver, silver alloys, etc.) and doped polysilicon, in an integrated circuit. Stress migration is the movement of atoms of the material from which the conductor is fabricated, leaving behind voids that enlarge over time, due to the stress of being confined within a more rigid structure such as an insulator, and more specifically an oxide.
FIG. 9 shows a scanning electron microscope photograph of a stress migration void 910 in an aluminum alloy trace or conductor 920 in an integrated circuit. In FIG. 9, the conductor is viewed from the top surface, either through a transparent/translucent oxide, or with the oxide removed. The stress migration void does not, at the time of the photograph, extend across the entire width of the conductor.
Stress migration voids enlarge over time as a function of the inverse cube of the width of a cross-section of the conductor. FIG. 10 illustrates a cross section of an aluminum alloy trace or conductor 1010 of width w and height h on a substrate illustrated as silicon wafer 1020, covered by a dielectric, such as a layer of silicon oxide 1040. A glue layer 1030 of titanium nitride on titanium may be employed to prevent the aluminum from diffusing into the silicon and also to better adhere the aluminum alloy conductor to the underlying substrate 1020.
As illustrated in FIG. 10, metal traces 1010 in integrated circuits are often formed on a semiconductor substrate 1020, such as silicon, with a so-called glue layer 1030 of another conductive material, such as titanium tungsten or titanium nitride, therebetween, as is known in the art. Layer 1030 is a layer that enhances the adherence of metal trace 1010 to substrate 1020 and prevents the reaction of the metal trace 1010 with substrate 1020. For a technology with a minimum line width of 0.5 microns, a metal trace 1010 is typically 0.5 microns thick (dimension h), and 0.5 microns wide (dimension w). In the same technology, layer 1040 is typically 0.5 microns thick (dimension t). Since both metal trace 1010 and layer 1030 are conductive, they form two parallel impedance paths for current conduction and results in a conduction path impedance that is the combined impedance of metal trace 1010 and layer 1030. Thus, even in the presence of a stress migration void in the metal trace 1010 that extends completely through a metal trace 1010, a conduction path can remain through layer 1030, albeit the impedance will be greater than if metal trace 1010 were available to provide a parallel current conduction path.
When a stress migration void is present in metal trace 1010, the impedance of the conduction path is impacted by the presence of the stress migration void. The impedance of the conduction path varies based on many factors, including but not limited to, whether stress migration voids are present, the extent to which stress migration voids that are present extend through the trace or glue layer, whether the trace is fabricated of one or more than one conduction paths, the sheet resistance or per unit impedance of the materials of which the conduction path is fabricated, and the height and width dimensions of the cross section of the conduction path or parallel conduction paths.
A need exists for a stress migration test structure and method of determining stress migration voids that can be used in manual or automated processes to determine the presence of stress migration voids in conduction paths such as traces on an integrated circuit. Such a stress migration test structure and method could be useful both at wafer test and package test. The stress migration test structure could be a stand-alone structure or could be a cell in an integrated circuit such that even after the integrated circuit is packaged, stress migration voids in the stress migration test structure within the integrated circuit could be evaluated. The number and severity of stress migration voids in the conductors of a stress migration test structure could be used as indicia to infer the viability of all conductors located on a chip, on a wafer, or on an integrated circuit.
In accordance with the present invention, a stress migration test structure is provided that can be used to detect stress migration defects such as voids in metal conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level, such as metal, of the circuitry on a die. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.